06694425 is referenced by 74 patents.
In a simultaneous multithread processor, a flush mechanism of a shared pipeline stage is disclosed. In the preferred embodiment, the shared pipeline stage happens to be one or all of the fetch stage, the decode stage, and/or the dispatch stage and the flush mechanism flushes instructions at the dispatch stage and earlier stages. The dispatch flush mechanism detects when an instruction of a particular thread is stalled at the dispatch stage of the pipelined processor. Subsequent instructions of that thread are flushed from all pipeline stages of the processor up to and including the dispatch stage. The dispatch stage is distinguished as being the stage in which all resources necessary for the successful dispatch of the instruction to the issue queues are checked. If a resource required only by that instruction is unavailable, then a dispatch flush is performed. Flush prioritization logic is available to determine if other flush conditions, including a previous dispatch flush, exist for that particular thread. If so, the flush prioritization logic will determine which flush, if any, should proceed. Those resources necessary for the successful dispatch and issuance of the instruction to the execution units but which are unavailable may be private or separate registers for each thread, may be special purpose or other non-renamed registers, or may be instructions for synchronized access to memory. This dispatch flush mechanism is more efficient than existing flush mechanisms which must flush throughout the processor pipelines up to and including the issue queues and execution units and result registers.