06614104 is referenced by 134 patents.

A semiconductor package includes a substrate and a semiconductor die wire bonded, or alternately flip chip bonded, to the substrate. The substrate includes three separate layers including a conductive layer having a pattern of conductive traces, a first insulating layer covering the conductive traces, and a second insulating layer covering the die. The insulating layers also include planar surfaces having external contacts, and conductive vias in electrical communication with the external contacts and with the conductive traces. The external contacts have matching patterns, such that the package can be stacked on a substantially identical package to form a stacked electronic assembly. In addition, the packages in the stacked assembly can have different circuit configurations, and can perform different functions in the assembly. A method for fabricating the package includes the steps of providing the conductive layer having the conductive traces, attaching the die to the conductive traces, forming the first insulating layer on the conductive layer, forming the second insulating layer on the die, forming the conductive vias through the insulating layers, and then forming the external contacts on the planar surfaces of the insulating layers.

Title
Stackable semiconductor package having conductive layer and insulating layers
Application Number
10/264047
Publication Number
6614104 (B2)
Application Date
October 4, 2002
Publication Date
September 2, 2003
Inventor
Mike Brooks
Caldwell
ID, US
Alan G Wood
Boise
ID, US
Warren M Farnworth
Nampa
ID, US
Agent
Stephen A Gratton
US
Assignee
Micron Technology
ID, US
IPC
H01L 23/02
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