06594730 is referenced by 16 patents.

An embodiment of the present invention provides a memory controller that includes a plurality of transaction queues and an arbiter, a prefetch cache in communication with the arbiter, and a prefetch queue in communication with the prefetch cache. The prefetch queue also may be provided in communication with each of the transaction queues for the purpose of determining whether the transaction queues are operating in a congested state.

Title
Prefetch system for memory controller
Application Number
9/365851
Publication Number
6594730 (B1)
Application Date
August 3, 1999
Publication Date
July 15, 2003
Inventor
Andrew V Anderson
Portland
OR, US
Herbert H J Hum
Portland
OR, US
Agent
Kenyon & Kenyon
US
Assignee
Intel Corporation
CA, US
IPC
G06F 13/00
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