06590816 is referenced by 142 patents.

The integrated memory has memory cells in a memory cell block having a plurality of column lines and a plurality of row lines. The row lines include regular row lines and redundant row lines. In the event of a read access to a current row line, a self-test unit checks the correctness of the memory cell contents read and, in the event of a defect, generates a defect signal for the current row line and, for each regular row line, detects the defects ascertained and compares them with an average defect for all of the regular row lines. When a predetermined repair condition is met during the comparison, the self-test unit outputs a row repair signal for the current row line. A self-repair unit interacting with the self-test unit replaces the current row line by a redundant row line in response to a row repair signal in the course of operation of the integrated memory. By still utilizing the existing redundancy after delivery, the failure probability of the memory module can be significantly reduced.

Title
Integrated memory and method for testing and repairing the integrated memory
Application Number
10/91076
Publication Number
6590816 (B2)
Application Date
March 5, 2002
Publication Date
July 8, 2003
Inventor
Martin Perner
M√ľnchen
US
Agent
Ralph E Locher
US
Werner H Stemer
US
Laurence A Greenberg
US
Assignee
Infineon Technologies
US
IPC
G11C 29/00
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