06590258 is referenced by 130 patents and cites 2 patents.

A composite, layered, integrated circuit formed by bonding of insulator layers on wafers provides for combination of otherwise incompatible technologies such as trench capacitor DRAM arrays and high performance, low power, low voltage silicon on insulator (SOI) switching transistors and short signal propagation paths between devices formed on respective wafer layers of a chip. In preferred embodiments, an SOI wafer is formed by hydrophilic bonding of a wafer over an integrated circuit device and then cleaving a layer of the second wafer away using implanted hydrogen and low temperature heat treatment. Further wafers of various structures and compositions may be bonded thereover and connections between circuit elements and connection pads in respective wafers made using short vias that provide fast signal propagation as well as providing more numerous connections than can be provided on chip edges.

Title
SIO stacked DRAM logic
Application Number
9/998318
Publication Number
6590258 (B2)
Application Date
December 3, 2001
Publication Date
July 8, 2003
Inventor
William R Tonti
Essex Junction
VT, US
Jack A Mandclman
Stormville
NY, US
William H L Ma
Fishkill
NY, US
Mark C Hakey
Fairfax
VT, US
Ramachandra Divakauni
Somers
NY, US
Agent
Whitham Curtis & Christofferson P C
US
Agent
Mark F Chadurjian
US
Assignee
International Business Machines Corporation
NY, US
IPC
H01L 27/01
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