06584481 is referenced by 4 patents.

A bit-serial multiplier and an infinite impulse response filter implemented therewith, both implemented on an FPGA, are described in various embodiments. The bit-serial multiplier includes function generators configured as a multiplicand memory, a multiplier memory, a product memory, a bit-serial multiplier, and a bit-serial adder. The function generators are arranged to perform bit-serial multiplication of values in the multiplier and multiplicand memories.

Title
FPGA implemented bit-serial multiplier and infinite impulse response filter
Application Number
10/215778
Publication Number
6584481 (B1)
Application Date
August 9, 2002
Publication Date
June 24, 2003
Inventor
Andrew J Miller
Surrey
US
Agent
Edel M Young
US
LeRoy D Maunu
US
Assignee
Xilinx
CA, US
IPC
G06F 17/10
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