06566177 is referenced by 164 patents and cites 1 patents.

A silicon on insulator (SOI) dynamic random access memory (DRAM) cell and array and method of manufacture. The memory cell includes a trench storage capacitor connected by a self aligned buried strap to a vertical access transistor. A buried oxide layer isolates an SOI layer from a silicon substrate. The trench capacitor is formed in the substrate and the access transistor is formed on a sidewall of the SOI layer. A polysilicon strap connected to the polysilicon plate of the storage capacitor provides a self-aligned contact to the source of the access transistor. Initially, the buried oxide layer is formed in the wafer. Deep trenches are etched, initially just through the SOI layer and the BOX layer. Protective sidewalls are formed in the trenches. Then, the deep trenches are etched into the substrate. The volume in the substrate is expanded to form a bottle shaped trench. A polysilicon capacitor plate is formed in the deep trenches and conductive polysilicon straps are formed in the trenches between the capacitor plates and the SOI sidewalls. Device regions are defined in the wafer and a sidewall gate is formed in the deep trenches. Shallow trenches isolation (STI) is used to isolate and define cells. Bitlines and wordlines are formed on the wafer.

Title
Silicon-on-insulator vertical array device trench capacitor DRAM
Application Number
9/427257
Publication Number
6566177 (B1)
Application Date
October 25, 1999
Publication Date
May 20, 2003
Inventor
Scott R Stiffler
Amenia
NY, US
Ghavam Ghavami Shahidi
Yorktown Heights
NY, US
Devendra K Sadana
Pleasantville
NY, US
Dan Moy
Bethel
CT, US
Jack A Mandelman
Stormville
NY, US
Bijan Davari
Mahopac
NY, US
Tze chiang Chen
Yorktown Heights
NY, US
Gary B Bronner
Stormville
NY, US
Carl J Radens
LaGrangeville
NY, US
Agent
H Daniel Schnurmann
US
Assignee
International Business Machines Corporation
NY, US
IPC
H01L 21/00
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