06532556 is referenced by 218 patents.

A multi-bit-per-cell memory reduces the effect of defects and data errors by scrambling data bits before writing data. The scrambling prevents storage of consecutive bits in the same memory cell. When a memory cell is defective or produces an error, the bits read from the memory cell do not create consecutive bit errors that would be noticeable or uncorrectable. An error or a defect in a multi-bit memory cell causes at most scattered bit errors. Scramblers in multi-bit-per-cell memories can include 1) hardwired lines crossing between an input port and an output port, 2) programmable wiring options, 3) a linear buffer where reads from the buffer use addresses with swapped bits, or 4) a buffer array that switches between incrementing a row address first and incrementing a column address first when accessing memory cells in the buffer array.

Title
Data management for multi-bit-per-cell memories
Application Number
9/492949
Publication Number
6532556 (B1)
Application Date
January 27, 2000
Publication Date
March 11, 2003
Inventor
Hock Chuen So
Redwood City
CA, US
Sau Ching Wong
Hillsborough
CA, US
Agent
David T Millers
US
Assignee
Multi Level Memory Technology
CA, US
IPC
G11C 29/00
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