06523102 is referenced by 277 patents and cites 2 patents.

An ASIC device embedded into the memory subsystem of a computing device used to accelerate the transfer of active memory pages for usage by the system CPU from either compressed memory cache buffer or the addition of a compressed disk subsystem for improved system cost and performance. The Compression Enhanced Dual In-line Memory Module of the present invention uses parallel lossless compression and decompression engines embedded into the ASIC device for improved system memory page density and I/O subsystem data bandwidth. In addition, the operating system software optimizes page transfers between compressed disk partitions, compressed cache memory and inactive/active page memory within the computer system. The disclosure also indicates preferred methods for initialization, recognition and operation of the ASIC device transparently within industry standard memory interfaces and subsystems. The system can interface to present operating system software and applications, which enable optimal usage for the compressed paging system memory environment. The integrated parallel data compression and decompression capabilities of the compactor ASIC mounted on industry standard memory modules, along with the software drivers and filters of the present invention keep recently used pages compressed in the system memory. Additional performance is gained by the transfer of compressed pages between the system memory and the disk and network subsystems. In addition, the present invention may reduce the amount of data transferred between distributed computers across the LAN or WAN by the transmission of compressed page data between remote systems or distributed databases.

Title
PARALLEL COMPRESSION/DECOMPRESSION SYSTEM AND METHOD FOR IMPLEMENTATION OF IN-MEMORY COMPRESSED CACHE IMPROVING STORAGE DENSITY AND ACCESS SPEED FOR INDUSTRY STANDARD MEMORY SUBSYSTEMS AND IN-LINE MEMORY MODULES
Application Number
9/550380
Publication Number
6523102 (B1)
Application Date
April 14, 2000
Publication Date
February 18, 2003
Inventor
Peter Geiger
Austin
TX, US
Manuel J Alvarez II
Austin
TX, US
Thomas A Dye
Austin
TX, US
Agent
Jeffrey C Hood
US
Assignee
Interactive Silicon
TX, US
IPC
G06F 12/02
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