06502179 is referenced by 1 patents.

A processor for performing calculations based on an instruction code, the number of bits of which is not an integer multiple of a byte. The instruction code is divided into higher order bits and lower order bits. The number of the lower order bits is an integer multiple of one byte. A memory stores the lower order bits in a lower order bit storage section and the higher order bits in a higher order bit storage section. The lower order bits and the corresponding higher order bits are read from the memory in the same cycle when generating the instruction code.

Title
Method and apparatus for compactly storing instruction codes
Application Number
9/768363
Publication Number
6502179 (B2)
Application Date
January 25, 2001
Publication Date
December 31, 2002
Inventor
Hiroshi Naritomi
Kasugai
US
Kazuya Taniguchi
Kasugai
US
Kunihiro Ohara
Kasugai
US
Yukisato Miyazaki
Kasugai
US
Hayato Isobe
Kasugai
US
Sumitaka Hibino
Kasugai
US
Masayuki Takeshige
Kasugai
US
Teruyoshi Kondo
Kasugai
US
Agent
Staas & Halsey
US
Assignee
Fujitsu
US
IPC
G06F 12/04
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