06492211 is referenced by 125 patents and cites 1 patents.

There is disclosed herein a unique fabrication sequence and the structure of a vertical silicon on insulator (SOI) bipolar transistor integrated into a typical DRAM trench process sequence. A DRAM array utilizing an NFET allows for an integrated bipolar NPN sequence. Similarly, a vertical bipolar PNP device is implemented by changing the array transistor to a PFET. Particularly, a BICMOS device is fabricated in SOI. The bipolar emitter contacts and CMOS diffusion contacts are formed simultaneously of polysilicon plugs. The CMOS diffusion contact is the plug contact from bitline to storage node of a memory cell.

Title
Method for novel SOI DRAM BICMOS NPN
Application Number
9/656819
Publication Number
6492211 (B1)
Application Date
September 7, 2000
Publication Date
December 10, 2002
Inventor
William R Tonti
Essex Junction
VT, US
W David Pricer
Charlotte
VT, US
Jack A Mandelman
Stormville
NY, US
Russell J Houghton
Essex Junction
VT, US
Ramachandra Divakaruni
Somers
NY, US
Agent
F William McLaughlin
US
Eugene I Shkurko
US
Mark F Chadurjian
US
Assignee
International Business Machines Corporation
NY, US
IPC
H01L 21/00
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