06483156 is referenced by 132 patents and cites 2 patents.

A double gated silicon-on-insulator (SOI) MOSFET is fabricated by using a mandrel shallow trench isolation formation process, followed by a damascene gate. The double gated MOSFET features narrow diffusion lines defined sublithographically or lithographically and shrunk, damascene process defined by an STI-like mandrel process. The double gated SOI MOSFET increases current drive per layout width and provides low out conductance.

Title
Double planar gated SOI MOSFET structure
Application Number
9/526857
Publication Number
6483156 (B1)
Application Date
March 16, 2000
Publication Date
November 19, 2002
Inventor
Jed H Rankin
Burlington
VT, US
Kirk D Peterson
Essex Junction
VT, US
Effendi Leobandung
Wappingers Falls
NY, US
Jerome B Lasky
Essex Junction
VT, US
John J Ellis Monaghan
Grand Isle
VT, US
John A Bracchitta
South Burlington
VT, US
James W Adkisson
Jericho
VT, US
Agent
Mark F Chadurjian
US
Eugene I Shkurko
US
Michael E Whitham
US
Assignee
International Business Machines Corporation
NY, US
IPC
H01L 29/76
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