06480954 is referenced by 255 patents and cites 4 patents.

A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration. The new configuration data may include off-chip or on-chip data. The present invention typically allocates at least one slice to user data memory and includes means for disabling access to at least one of the N memory cells.

Title
Method of time multiplexing a programmable logic device
Application Number
9/876745
Publication Number
6480954 (B2)
Application Date
June 6, 2001
Publication Date
November 12, 2002
Inventor
Jennifer Wong
Fremont
CA, US
Robert Anders Johnson
San Jose
CA, US
Richard A Carberry
Los Gatos
CA, US
Stephen M Trimberger
San Jose
CA, US
Agent
Jeanette S Harms
US
Assignee
Xilinx
CA, US
IPC
G06F 9/00
View Original Source