06475869 is referenced by 343 patents.

A method of manufacturing an integrated circuit with a channel region containing germanium. The method can provide a double planar gate structure. The gate structure can be provided over lateral sidewalls of channel region. The semiconductor material containing germanium can increase the charge mobility associated with the transistor. An epitaxy process can form the channel region. A silicon-on-insulator can be used.

Title
Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
Application Number
9/793055
Publication Number
6475869 (B1)
Application Date
February 26, 2001
Publication Date
November 5, 2002
Inventor
Bin Yu
Sunnyvale
CA, US
Agent
Foley & Lardner
US
Assignee
Advanced Micro Devices
CA, US
IPC
H01L 21/336
View Original Source