06470489 is referenced by 354 patents and cites 5 patents.

A method for performing design rule checking on OPC corrected or otherwise corrected designs is described. This method comprises accessing a corrected design and generating a simulated image. The simulated image corresponds to a simulation of an image which would be printed on a wafer if the wafer were exposed to an illumination source directed through the corrected design. The characteristics of the illumination source are determined by a set of lithography parameters. In creating the image, additional characteristics can be used to simulate portions of the fabrication process. However, what is important is that a resulting simulated image is created. The simulated image can then be used by the design rule checker. Importantly, the simulated image can be processed to reduce the number of vertices in the simulated image, relative to the number of vertices in the OPC corrected design layout. Also, the simulated image can be compared with an idea layout image, the results of which can then be used to reduce the amount of information that is needed to perform the design rule checking.

Title
Design rule checking system and method
Application Number
9/153783
Publication Number
6470489 (B1)
Application Date
September 16, 1998
Publication Date
October 22, 2002
Inventor
Yagyensh C Pati
Redwood City
CA, US
Yao Ting Wang
Sunnyvale
CA, US
Fang Cheng Chang
Mountain View
CA, US
Agent
Haynes Beffel & Wolfeld
US
Agent
Mark A Haynes
US
Assignee
Numerical Technologies
CA, US
IPC
G06F 17/50
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