06426900 is referenced by 29 patents and cites 3 patents.

A DLL circuit generates a control clock specifying an operating timing of a data output buffer according to an external clock. The DLL circuit includes a replica delay time adjusting section and a phase control section. The phase control section controls such that a feedback clock and the external clock becomes in phase. The replica delay time adjusting section adjusts a delay time of the feedback clock behind the control clock according to an operating condition serving as a factor for changing a processing time of the data output buffer.

Title
Synchronous semiconductor memory device performing data output in synchronization with external clock
Application Number
9/907589
Publication Number
6426900 (B1)
Application Date
July 19, 2001
Publication Date
July 30, 2002
Inventor
Seiji Sawada
Hyogo
US
Yukiko Maruyama
Hyogo
US
Agent
McDermott Will & Emery
US
Assignee
Mitsubishi Denki Kabushiki Kaisha
US
IPC
G11C 7/00
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