06425112 is referenced by 197 patents.

A method and computer system are provided for checking integrated circuit designs for design rule violations. The method may include generating a working design data set, creating a wafer image data set, comparing the wafer image data set to the design rules to produce an error list and automatically altering the working design data set when the comparing indicates a design rule violation. The method further automatically repeats the creating, the comparing and the automatically altering until no design rule violations occur or no solution to the errors exists.

Title
Auto correction of error checked simulated printed images
Application Number
9/335305
Publication Number
6425112 (B1)
Application Date
June 17, 1999
Publication Date
July 23, 2002
Inventor
William C Leipold
Enosburg Falls
VT, US
Edward W Conrad
Jeffersonville
VT, US
Daniel C Cole
Jericho
VT, US
Orest Bula
Shelburne
VT, US
Agent
Richard M Kotulak Esq
US
McGinn & Gibb PLLC
US
Assignee
International Business Machines Corporation
NY, US
IPC
E06F 17/50
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