06368896 is referenced by 151 patents.

A chip scale semiconductor package and a method for fabricating the package are provided. The package includes a semiconductor die and a flex circuit bonded to the face of the die. The flex circuit includes a polymer substrate with a dense array of external contacts, and a pattern of conductors in electrical communication with the external contacts. The package also includes interconnects configured to provide separate electrical paths between die contacts (e.g., bond pads), and the conductors on the flex circuit. Several different embodiments of interconnects are provided including: bumps on the die contacts, bonded to the flex circuit conductors with a conductive adhesive layer; polymer bumps on the conductors, or die contacts, applied in a semi-cured state and then fully cured; solder bumps on the die contacts and conductors, bonded to one another using a bonding tool; rivet-like bonded connections between the conductors and die contacts, formed using metal bumps and a wire bonding or ball bonding apparatus; single point bonded connections between the conductors and die contacts, formed with a bonding tool; and wire bonds between the conductors and die contacts.

Title
Method of wafer level chip scale packaging
Application Number
9/298514
Publication Number
6368896 (B2)
Application Date
April 23, 1999
Publication Date
April 9, 2002
Inventor
Mike Brooks
Caldwell
ID, US
Alan G Wood
Boise
ID, US
Warren M Farnworth
Nampa
ID, US
Agent
Stephen A Gratton
US
Assignee
Micron Technology
ID, US
IPC
H01L 21/44
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