06355501 is referenced by 381 patents.

An assembly consisting of three dimensional stacked SOI chips, and a method of forming such integrated circuit assembly, each of the SOI chips including a handler making mechanical contact to a first metallization pattern making electrical contact to a semiconductor device. The metalized pattern, in turn, contacts a second metallization pattern positioned on an opposite surface of the semiconductor device. The method of fabricating the three-dimensional IC assembly includes the steps of: a) providing a substrate having a third metalized pattern on a first surface of the substrate; b) aligning one of the SOI chips on the first surface of the substrate, by having the second metallization pattern of the SOI chip make electrical contact with the third metalized pattern of the substrate; c) removing the handler from the SOI chip, exposing the first metallization pattern of the SOI chip; d) aligning a second one of the SOI chips with the first SOI chip, having the second metallization pattern of the second SOI chip make electrical contact to the exposed first metallization pattern of the first SOI chip; and e) repeating steps c) and d) for mounting subsequent SOI chips one on top of the other.

Title
Three-dimensional chip stacking assembly
Application Number
9/666767
Publication Number
6355501 (B1)
Application Date
September 21, 2000
Publication Date
March 12, 2002
Inventor
H Bernhard Pogge
Hopewell Junction
NY, US
Ka Hing Fung
Beacon
NY, US
Agent
H Daniel Schnurmann
US
Assignee
International Business Machines Corporation
NY, US
IPC
H01L 21/44
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