06338106 is referenced by 95 patents and cites 21 patents.

A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be connected to the bus system (for cascading).

Title
I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures
Application Number
9/335974
Publication Number
6338106 (B1)
Application Date
June 18, 1999
Publication Date
January 8, 2002
Inventor
Robert Münch
Karlsruhe
US
Martin Vorbach
Karlsruhe
US
Agent
Kenyon & Kenyon
US
Assignee
PACT
US
IPC
G06F 13/00
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