06330296 is referenced by 17 patents and cites 12 patents.

The present invention provides a delay-locked loop (DLL). The DLL comprises a phase-frequency detector (PFD) for receiving a reference signal. The DLL further includes a charge pump which is coupled to the PFD. The DLL also includes a loop filter which is coupled to the charge pump and the PFD. Additionally in the DLL, delay line means is coupled to the charge pump and the loop filter. The delay line means provides a feedback signal to the PFD. The DLL further includes monitor means coupled to the PFD, the charge pump and the loop filter. The monitor means is for detecting when a voltage across the loop filter is at a predetermined level, wherein when the voltage is at the predetermined level the monitor means causes the PFD to enter a pump-down mode until the feedback signal is aligned with the reference signal. An advantage of the present invention is that DLL loop tracking failures based upon a stuck condition are reliably avoided. Specifically, the DLL in accordance with the present invention can reliably recover from the stuck condition in which the adjustable delay is at its lower limit and the PFD asserts the UP control signal. Additionally, the DLL is cost effective and is easily implemented utilizing existing processes.

Title
Delay-locked loop which includes a monitor to allow for proper alignment of signals
Application Number
9/97130
Publication Number
6330296 (B1)
Application Date
June 12, 1998
Publication Date
December 11, 2001
Inventor
David John Seman
Cary
NC, US
James Norris Dieffenderfer
Apex
NC, US
George Diniz
Liberty
NC, US
Francois Ibrahim Atallah
Raleigh
NC, US
Agent
Sawyer Law Group
US
Assignee
International Business Machines Corporation
NY, US
IPC
H03D 3/24
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