06326697 is referenced by 186 patents and cites 33 patents.

Integrated circuit devices produced by a method in which devices are formed and packaged at the wafer scale. The integrated circuit device includes bond pads on a first side thereof, a layer of glass adhesively affixed to the first side, a layer of sealant covering the second side and edges thereof, and a metallization pattern on the layer of glass connected via an array of contact holes to the bond pads on the integrated circuit device. The device is advantageously formed with an etchable glass package and palladium metallization pattern.

Title
Hermetically sealed chip scale packages formed by wafer level fabrication and assembly
Application Number
9/208906
Publication Number
6326697 (B1)
Application Date
December 10, 1998
Publication Date
December 4, 2001
Inventor
Warren M Farnworth
Nampa
ID, US
Agent
TraskBritt
US
Assignee
Micron Technology
ID, US
IPC
H01L 21/44
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