06322903 is referenced by 483 patents and cites 94 patents.

A first level packaging wafer is made of a semiconductor or insulating material. The bumps on the wafer are made using vertical integration technology, without solder or electroplating. More particularly, vias are etched part way into a first surface of the substrate. Metal is deposited into the vias. Then the substrate is blanket-etched from the back side until the metal is exposed and protrudes from the vias to form suitable bumps. Dicing methods and vertical integration methods are also provided. Solder or electroplating are used in some embodiments.

Title
Package of integrated circuits and vertical integration
Application Number
9/456225
Publication Number
6322903 (B1)
Application Date
December 6, 1999
Publication Date
November 27, 2001
Inventor
Sergey Savastiouk
San Jose
CA, US
Oleg Siniaguine
San Jose
CA, US
Agent
Skjerven Morrill MacPherson
US
Agent
Michael Shenker
US
Assignee
Tru Si Technologies
CA, US
IPC
H01L 21/44
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