06321366 is referenced by 126 patents and cites 124 patents.

The disclosed devices are several forms of a timing insensitive glitch-free (TIGF) logic device. The TIGF logic device can take the form of any latch or edge-triggered flip-flop. In one embodiment, a trigger signal is provided to update the TIGF logic device. The trigger signal is provided during a short trigger period that occurs at adjacent times from the evaluation period. In latch form, the TIGF latch includes a flip-flop that holds the current state of the TIGF latch until a trigger signal is received. A multiplexer is also provided to receive the new input value and the old stored value. The enable signal functions as the selector signal for the multiplexer. Because the trigger signal controls the updating of the TIGF latch, the data at D input to the TIGF latch and the control data at the enable input can arrive in any order without suffering from hold time violations. Also, because the trigger signal controls the TIGF updates, the enable signal can glitch often without negatively affecting the proper operation of the TIGF latch. In flip-flop form the TIGF flip-flop includes a first flip-flop that holds the new input value, a second flip-flop that holds the current stored value, and a clock edge detector. All three of these components are controlled by the trigger signal for updating the TIGF flip-flop. A multiplexer is also provided with the edge detector signal functioning as the selector signal. Because one dedicated first flip-flop stores the new input value which effectively blocks input changes during evaluation, hold time violations are avoided. With the trigger signal controlling the TIGF flip-flop updates, clock glitches do not affect the hardware model of the user design circuit that uses the TIGF flip-flop as the emulated flip-flop.

Title
Timing-insensitive glitch-free logic system and method
Application Number
9/144222
Publication Number
6321366 (B1)
Application Date
August 31, 1998
Publication Date
November 20, 2001
Inventor
Quincy Kun Hsu Shen
Union City
CA, US
Sharon Sheau Ping Lin
Cupertino
CA, US
Ping Sheng Tseng
Sunnyvale
CA, US
Agent
Oppenheimer Wolff & Donnelly
US
Agent
Chien Chou
US
Assignee
Axis Systems
CA, US
IPC
G06F 17/50
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