06317350 is referenced by 114 patents and cites 13 patents.

A method and apparatus hierarchically cascades a number of memory devices to achieve a balance between the number of match flag inputs and the time required to generate the system match flag. In some embodiments, the number of match inputs required for each cascaded device and the time required to generate a system match flag are each logarithmically related to the number of cascaded devices. In one embodiment, an m-level hierarchy of groups are defined for up to n memory devices, where m=log

2

n and m is an integer greater than 2. The first hierarchy is defined as including n/2 groups of 2 memory devices, the second hierarchy is defined as including n/4 groups of 4 memory devices, and so on, until a final hierarchy of one group is defined. Each group in a given hierarchical level includes a pair of groups from the preceding hierarchical level. At each hierarchical level, the match flag generated by the first of the group's pair may be provided to each of the CAM devices in the second of the group's pair. In other embodiments, at each hierarchical level, the match flag(s) generated by devices in the first of the pair defined in the previous hierarchical are selectively provided to devices in the second of the pair defined in the previous hierarchical level.

Title
Hierarchical depth cascading of content addressable memory devices
Application Number
9/595850
Publication Number
6317350 (B1)
Application Date
June 16, 2000
Publication Date
November 13, 2001
Inventor
Varadarajan Srinivasan
Los Altos Hills
CA, US
Jose Pio Pereira
Santa Clara
CA, US
Agent
William L Paradice III
US
Assignee
NetLogic Microsystems
CA, US
IPC
G11C 15/00
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