06298420 is referenced by 12 patents and cites 12 patents.

Method and apparatus for processing serial bus read requests in a memory controller when the memory controller interfaces to both a pipelined bus and a serial bus. According to the method, the read request message is received and is split into several atomic transactions. The atomic transactions are issued on the pipelined bus. Data related to the several atomic transactions is stored in a queue. The requested data is read from the queue and placed in a response message on the serial bus.

Title
Coherent variable length reads from system memory
Application Number
9/567139
Publication Number
6298420 (B1)
Application Date
May 8, 2000
Publication Date
October 2, 2001
Inventor
Jonathan Nick Spitz
Portland
OR, US
Sin Sim Tan
Hillsboro
OR, US
Chih Cheh Chen
Hillsboro
OR, US
Suresh Chittor
Hillsboro
OR, US
Agent
Kenyon & Kenyon
US
Assignee
Intel Corporation
CA, US
IPC
G06F 12/02
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