06294936 is referenced by 38 patents and cites 12 patents.

A spread-spectrum modulation method and circuit for a clock generator phase-locked loop (PLL). A dither signal is injected into a PLL in synchronization with and having the same period or fraction of the same period as the phase comparison performed within the PLL. Over such period, the phase error caused by the modulation will integrate to zero and hence avoid transmitting a disturbance to the loop. A particular embodiment utilizes an output of the reference divider and/or feedback divider within the PLL to generate the dither signal. Such a configuration avoids the need for additional hardware which otherwise would increase the chip area and/or cost of the device. The reference divider and/or feedback divider is made up preferably of a linear feedback shift register (LFSR). One or more stages of the LFSR provide an output which is used to generate the dither signal. In a preferred embodiment, the output from the LFSR exhibits a pseudo-random sequence.

Title
Spread-spectrum modulation methods and circuit for clock generator phase-locked loop
Application Number
9/161969
Publication Number
6294936 (B1)
Application Date
September 28, 1998
Publication Date
September 25, 2001
Inventor
Daniel M Clementi
Doylestown
PA, US
Agent
Renner Otto Boisselle & Sklar
US
Assignee
American Microsystems
ID, US
IPC
H03D 1/04
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