06292705 is referenced by 40 patents and cites 36 patents.

A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased bandwidth between processors and shared memory. A Transaction Controller, Transaction Bus, and Transaction Status Bus are used for serialization, centralized cache control, and highly pipelined address transfers. The shared Transaction Controller serializes transaction requests from Initiator devices that can include CPU/Cache modules and Peripheral Bus modules. The Transaction Bus of an illustrative embodiment is implemented using segmented buses, distributed muxes, point-to-point wiring, and supports transaction processing at a rate of one transaction per clock cycle. The Transaction Controller monitors the Transaction Bus, maintains a set of duplicate cache-tags for all CPU/Cache modules, maps addresses to Target devices, performs centralized cache control for all CPU/Cache modules, filters unnecessary Cache transactions, and routes necessary transactions to Target devices over the Transaction Status Bus. The Transaction Status Bus includes both busbased and point-to-point control of the target devices. A modified rotating priority scheme is used to provide Starvation-free support for Locked buses and memory resources via backoff operations. Speculative memory operations are supported to further enhance performance.

Title
Method and apparatus for address transfers, system serialization, and centralized cache and transaction control, in a symetric multiprocessor system
Application Number
9/163294
Publication Number
6292705 (B1)
Application Date
September 29, 1998
Publication Date
September 18, 2001
Inventor
Daniel Fu
Sunnyvale
CA, US
Brian R Baird
Pleasanton
CA, US
Earl T Cohen
Fremont
CA, US
Xiaofan Wei
Sunnyvale
CA, US
Zong Yu
Cupertino
CA, US
Yuanlong Wang
Sunnyvale
CA, US
Agent
Kelly H Hale
US
Keith Kind
US
Assignee
Conexant Systems
CA, US
IPC
G05B 19/18
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