An improved spread spectrum clock generator circuit is provided which automatically compensates for variations in passive component values and system gain and charge pump current in a Phase Locked Loop circuit. The pulse widths of the UP and DOWN outputs of the Phase Frequency Detector are monitored at particular intervals to determine the deviation error of these UP and DOWN signals, as compared to typical or nominal pulse-width durations. After an error is determined in the actual values of the pulse-width durations, the Phase Locked Loop (PLL) system is adjusted depending upon the magnitude and direction of the error signal. Changes in the PLL gain parameters, especially the VCO gain and charge pump current, have a significant effect on the PFD outputs, such that the width of the UP and DOWN signals vary as the frequency changes along the spread spectrum profile. At one portion of the spread spectrum profile, the “peak” (i.e., maximum) pulse width of these UP and DOWN signals will be a function of the spread spectrum's modulation profile and the PLL parameters. In addition to sampling for maximum pulse widths at the profile locations exhibiting peaks and valleys, the actual error profile may also exhibit a similarly large deviation from the target error profile at times just before the occurrence of the maximum peak and minimum peak (or “valley”). While determining precisely where within the profile these other substantial deviations occur is more difficult than monitoring the same signals at their maximum peaks, there are certain advantages to using the alternative locations along the error profile, which are described below.