A fabrication method is disclosed for fabricating a memory cell comprised of three regions of a first-type deposited on a substrate of a second-type, a first insulating layer deposited over the substrate, a floating gate disposed over the first insulating layer, a second insulating layer disposed over the floating gate and the first insulating layer, a control gate disposed over the second insulating layer and partially extending over the floating gate, and a select gate disposed over the second insulating layer. The memory cell can be configured in four different ways. When placed in a memory array, a predefined number of memory cells can be grouped into blocks. By using a byte(block)-select transistor, the memory cells can be accessed and altered on block by block basis. The novel memory cells can be manufactured without requiring additional processing steps aside from those required in the manufacturing of the comparable flash memory cells.