06282694 is referenced by 11 patents and cites 6 patents.

An EDA tool is provided with a floorplan generator to automatically generate an optimized floorplan for an IC design having a number of design blocks. The floorplanner generates an initial O-tree representation for the design blocks. The floorplanner then perturbs the O-tree representation to seek an alternate O-tree representation that represents an optimized placement of the design blocks in accordance with a cost function. The floorplanner performs the perturbation systematically for all design blocks, traversing the O-tree representation in a depth-first manner and removing one design block at a time. In one embodiment, for each removed design block, the floorplanner also seeks an appropriate re-insertion point for the removed design block systematically by traversing a reduced version of the O-tree representation augmented with candidate insertion points in a depth-first manner. Under the present invention, ceiling and floor contours as well as contour pointers are employed to improve the efficiency of the traversing iterations.

Title
IC design floorplan generation using ceiling and floor contours on an O-tree structure
Application Number
9/336529
Publication Number
6282694 (B1)
Application Date
June 18, 1999
Publication Date
August 28, 2001
Inventor
Pei Ning Guo
765 Erie Cir., Milpitas
CA, US
Chung Kuan Cheng
4407 Mensha Pl., San Diego
CA, US
Agent
Columbia IP Law Group PC
US
IPC
G06F 17/50
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