06282145 is referenced by 104 patents and cites 90 patents.

Memory array architectures and operating methods suitable for super high density in the giga bits for multilevel nonvolatile memory integrated circuit system. The array architectures and operating methods include: (1) an Inhibit and Select Segmentation Scheme; (2) a Multilevel Memory Decoding Scheme that includes a Power Supply Decoded Decoding Scheme, a Feedthrough-to-Memory Decoding Scheme, a Feedthrough-to-Driver Decoding Scheme, and a Winner-Take-All Kelvin Memory Decoding Scheme; (3) a constant-total-current-program scheme; (4) includes fast-slow and 2-step ramp rate control programming; and a reference system method and apparatus, which includes a Positional Linear Reference System, a Positional Geometric Reference System, and a Geometric Compensation Reference System. The apparatus and method enable multilevel programming, reading, and margining.

Title
Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system
Application Number
9/231928
Publication Number
6282145 (B1)
Application Date
January 14, 1999
Publication Date
August 28, 2001
Inventor
George J Korsh
Redwood City
CA, US
Sakhawat M Khan
Sunnyvale
CA, US
Hieu Van Tran
San Jose
CA, US
Agent
Gray Cary Ware & Freidenrich
US
Assignee
Silicon Storage Technology
CA, US
IPC
G11C 8/00
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