06275051 is referenced by 60 patents and cites 8 patents.

An apparatus for simultaneously testing or burning in a large number of the integrated circuit chips on a product wafer includes probes mounted on a first board and tester chips mounted on a second board, there being electrical connectors connecting the two boards. The tester chips are for distributing power to the product chips or for testing the product chips. The probes and thin film wiring to which they are attached are personalized for the pad footprint of the particular wafer being probed. The base of the first board and the second board both remain the same for all wafers in a product family. The use of two boards provides that the tester chip is kept at a substantially lower temperature than the product chips during burning to extend the lifetime of tester chips. A gap can be used as thermal insulation between the boards, and the gap sealed and evacuated for further thermal insulation. Evacuation also provides atmospheric pressure augmentation of contact for connection between boards and contact to wafer. Probes for parallel testing of chips are arranged in crescent shaped stripes to significantly increase tester throughput as compared with probes arranged in an area array.

Title
Segmented architecture for wafer test and burn-in
Application Number
9/240121
Publication Number
6275051 (B1)
Application Date
January 29, 1999
Publication Date
August 14, 2001
Inventor
Wade H White
Hyde Park
NY, US
Joseph J Van Horn
Underhill
VT, US
Roger R Schmidt
Poughkeepsie
NY, US
Charles H Perry
Poughkeepsie
NY, US
Mark R Laforce
Essex Junction
VT, US
Paul M Gaschke
Wappingers Falls
NY, US
David L Gardell
Fairfax
VT, US
James M Crafts
Warren
VT, US
Dennis R Conti
Essex Junction
VT, US
Dennis R Barringer
Walkill
NY, US
Thomas W Bachelder
Swanton
VT, US
Agent
Robert A Walsh
US
William N Hogg
US
Assignee
International Business Machines Corporation
NY, US
IPC
G01R 1/073
View Original Source