06274291 is referenced by 1 patents and cites 16 patents.

A technique is provided for forming a circuitized substrate which substantially reduces defects in a circuit board formed of multiple layers of dielectric material on each of which layers electrical circuitry is formed. Each layer of dielectric material is formed of two distinct and separate coatings or sheets or films of a photopatternable dielectric material which is photoformed to provide through openings to the layer of circuitry below and then plated with the desired circuitry including plating in the photoformed openings to form vias. In this way if there is a pin hole type defect in either coating or sheet of dielectric material, in all probability it will not align with a similar defect in the other sheet or coating of the dielectric layer, thus preventing unwanted plating extending from one layer of circuitry to the underlying layer of circuitry.

Title
Method of reducing defects in I/C card and resulting card
Application Number
9/195010
Publication Number
6274291 (B1)
Application Date
November 18, 1998
Publication Date
August 14, 2001
Inventor
John A Welsh
Binghamton
NY, US
Kenneth Lynn Potter
Kirkwood
NY, US
Mary Beth Fletcher
Vestal
NY, US
John C Camp
Owego
NY, US
Ashwinkumar C Bhatt
Endicott
NY, US
Agent
William N Hogg
US
Assignee
International Business Machines Corporation
NY, US
IPC
G03F 7/00
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