06272668 is referenced by 51 patents and cites 30 patents.

A method for improving the timing performance of a standard cell ASIC layout. The method is operable at any phase of the ASIC design cycle including following the completion of layout phase placement and routing. The method compares post-layout timing values with pre-layout timing targets for each timing arc associated with each standard cell component of the ASIC design. For each timing arc, a functionally equivalent cell having higher or lower output drive is selected which optimally improves the timing slack on each timing arc. To assure that the method converges and terminates, a list of timing slack values, one for each timing arc of the ASIC design, is constructed in sorted order from worst timing slack to best timing slack. The swap method determines in order from worse timing slack to best a functionally equivalent standard cell which may be swapped to improve the timing slack on the timing arc. Once a standard cell is swapped for a given timing arc, no further swaps need be made for subsequent entries on the sorted list: the timing slack of subsequent entries is assured to be better than the worse timing slack value of an earlier encountered timing arc in the sorted list.

Title
Method for cell swapping to improve pre-layout to post-layout timing
Application Number
9/318388
Publication Number
6272668 (B1)
Application Date
May 25, 1999
Publication Date
August 7, 2001
Inventor
Andres R Teene
Fort Collins
CO, US
Agent
Townsend and Townsend and Crew
US
Assignee
NCR Corporation
OH, US
Hyundai Electronics America
CA, US
IPC
G06F 17/50
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