06272579 is referenced by 85 patents and cites 28 patents.

A system and method for transferring data in a multiprocessor architecture capable of supporting multiple processors. The system comprises a priority assignor that provides a dynamic priority to input/output unit (IOU), D-cache and I-cache devices requests as a function of an intrinsic priority assigned to each device and a plurality of factors including the existence of a row match between a requested address and a previously serviced request, the number of times a device has been denied service and the number of times a device has been serviced without interruption. The system also includes a tracker to keep track of the number of times each of the factors occurs and a priority changer to change the priority of the devices as a function of the intrinsic priority and the number.

Title
Microprocessor architecture capable of supporting multiple heterogeneous processors
Application Number
9/253761
Publication Number
6272579 (B1)
Application Date
February 22, 1999
Publication Date
August 7, 2001
Inventor
Le Trong Nguyen
Monte Sereno
CA, US
Cheng Long Tang
San Jose
CA, US
Te Li Lau
Palo Alto
CA, US
Yasuaki Hagiwara
Santa Clara
CA, US
Derek J Lentz
Los Gatos
CA, US
Agent
Sterne Kessler Goldstein & Fox P L L C
US
Assignee
Seiko Epson Corporation
US
IPC
G06F 13/14
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