06255849 is referenced by 179 patents and cites 6 patents.

An on-chip method for self-modifying a programmable logic device (PLD) including a plurality of configurable logic blocks (CLBs), a plurality of interconnect resources for selectively connecting the CLBs, and a block memory circuit selectively connected to the interconnect resources. The CLBs are configured to implement a reconfigurable functional portion and a configuration control portion. A logic function is performed by the reconfigurable functional portion in accordance with first configuration data, while the configuration control portion monitors operation data signals transmitted to or from the reconfigurable functional portion. When the configuration control portion detects a need to modify the configuration of the reconfigurable functional portion, the configuration control portion transmits read instructions (e.g., address information) to the block memory circuit, thereby causing the block memory circuit to transmit modified configuration data to the reconfigurable functional portion, thereby performing self-modification of the PLD using only on-chip resources. In one embodiment, the configuration control portion processes the transmitted operation data received from the reconfigurable functional portion, generates the modified configuration data, and transmits the modified configuration data to the block memory circuit, where the modified configuration data is temporarily stored before transmission to the reconfigurable functional portion.

Title
On-chip self-modification for PLDs
Application Number
9/498938
Publication Number
6255849 (B1)
Application Date
February 4, 2000
Publication Date
July 3, 2001
Inventor
Sundararajarao Mohan
Cupertino
CA, US
Agent
Patrick T Bever
US
Assignee
Xilinx
CA, US
IPC
H03K 19/177
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