06249855 is referenced by 12 patents and cites 4 patents.

An arbiter system for the instruction issue logic of a CPU has at least two encoder circuits that select instructions in an instruction queue for issue to first and second execution units, respectively, based upon the positions of the instructions within the queue and requests by the instructions for the first and/or second execution units. As a result, since the instruction can request different execution units, this system is compatible with architectures where the execution units may have different capabilities to execute different instructions, i.e., each integer execution unit may not be able to execute all of the instructions in the CPU's integer instruction set. According to the present invention, one of the encoder circuits is subordinate to the other circuit. The subordinate encoder circuit selects instructions from the instruction queue based not only on the positions of the instructions and their requests, but the instruction selection of the dominant encoder circuit.

Title
Arbiter system for central processing unit having dual dominoed encoders for four instruction issue per machine cycle
Application Number
9/89474
Publication Number
6249855 (B1)
Application Date
June 2, 1998
Publication Date
June 19, 2001
Inventor
Bruce A Gieseke
San Jose
CA, US
James A Farrell
Harvard
MA, US
Agent
Hamilton Brook Smith & Reynolds P C
US
Assignee
Compaq Computer Corporation
TX, US
IPC
G06F 9/38
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