06243140 is referenced by 22 patents and cites 20 patents.

Methods and apparatus for reducing the total amount of memory required to implement a video decoder and to perform a scan conversion operation on decoded video are described. In accordance with the present invention this is accomplished by having an interlaced to progressive (I-P) conversion circuit utilize the same frame memory used to decode the images upon which a conversion operation is performed. In this manner, the images, e.g., frames, which are buffered in the decoder are utilized by both the decoder and I-P conversion circuit thereby eliminating the need for the I-P conversion circuit to be supported with an independent frame memory. Data included in a decoder's frame memories is used to detect moving image areas for purposes of the I-P conversion process. In a specific exemplary embodiment, one of three frames, which is nearest to a present frame, is referred for calculating frame difference signals. Both subsequent and preceding frames are used to detect motion for I-P conversion purposes. This approach eliminates the need for a separate frame memory for motion detection purposes. Using the above discussed memory saving techniques, I-P conversion can be performed in accordance with the present invention by sharing the anchor frame memories and B-frame buffer present in a conventional decoder for both decoding and I-P conversion.

Methods and apparatus for reducing the amount of buffer memory required for decoding MPEG data and for performing scan conversion
Application Number
Publication Number
6243140 (B1)
Application Date
February 17, 1999
Publication Date
June 5, 2001
Norihiro Suzuki
Straub & Pokotylo
Michael P Straub
Hitachi America
H04N 7/01
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