06242945 is referenced by 90 patents and cites 11 patents.

A field programmable gate array (FPGA) having a plurality of configurable logic blocks (CLBs). Each of the CLBs includes programmable interconnect resources, a field programmable configurable logic element (CLE) circuit and a corresponding non-field programmable gate array. The programmable interconnect resources are programmed to selectively couple or decouple each CLE circuit from its corresponding non-field programmable gate array. Dedicated interconnect resources enable adjacent non-field programmable gate arrays to be coupled. By coupling adjacent non-field programmable gate arrays, one or more relatively large non-field programmable gate arrays can be formed. The non-field programmable gate arrays have a greater logic density than the CLE circuits, thereby providing an improved logic density to the CLBs. Moreover, because each CLB includes a non-field programmable gate array, each of the CLE circuits is readily connectable to a non-field programmable gate array. The non-field programmable gate array can be used to provide a plurality of mask-programmable input/output driver circuits for connection to the pads of the FPGA.

Title
Field programmable gate array with mask programmable I/O drivers
Application Number
9/589146
Publication Number
6242945 (B1)
Application Date
June 7, 2000
Publication Date
June 5, 2001
Inventor
Bernard J New
Los Gatos
CA, US
Agent
Edel M Young
US
E Eric Hoffman Esq
US
Assignee
Xilinx
CA, US
IPC
G06F 7/38
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