06240040 is referenced by 159 patents and cites 6 patents.

An address buffering and decoding architecture for a multiple bank (or N bank) simultaneous operation flash memory is described. For the duration of a read operation at one bank of the N banks, a write operation can only be performed on any one of the other N-1 banks. For the duration of a write operation at one bank of the N banks, a read operation can only be performed on any one of the other N-1 banks. The address buffering and decoding architecture includes a control logic circuit, an address selection circuit located at each of the N banks, and address buffer circuitry. The control logic circuit is used to generate N read select signals to select one bank of the N banks for a read operation and N write select signals to select another bank of the N banks for a write operation. Each address selection circuit is configured to receive from the control logic circuit a respective one of the N read select signals and a respective one of the N write select signals. The address buffer circuitry is used to simultaneously provide a write address and a read address in order to access core memory cells. Respective first portions of the write and read addresses are provided to the control logic circuit to generate the respective N read select signals and N write select signals. Respective second portions of the write and read addresses are provided to the respective address selection circuit.

Title
Multiple bank simultaneous operation for a flash memory
Application Number
9/526239
Publication Number
6240040 (B1)
Application Date
March 15, 2000
Publication Date
May 29, 2001
Inventor
Kendra Nguyen
San Jose
CA, US
Lee Edward Cleveland
Santa Clara
CA, US
Takao Akaogi
Cupertino
CA, US
Agent
Brinks Hofer Gilson & Lione
US
Assignee
Fujitsu
US
Advanced Micro Devices
CA, US
IPC
G11C 8/00
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