06235554 is referenced by 388 patents and cites 45 patents.

A stackable chip scale semiconductor package and a method for fabricating the package are provided. The package includes a substrate having a die mounting site wherein a semiconductor die is mounted. The package also includes first contacts formed on a first surface of the substrate, and second contacts formed on an opposing second surface of the substrate. Conductive vias in the substrate electrically connect the first contacts to the second contacts. In addition, the first contacts and the second contacts have a mating configuration, such that a second package can be stacked on and electrically connected to the package. The method for fabricating the package includes the steps of: laser machining and etching the vias, forming an insulating layer in the vias, and then depositing a conductive material within the vias.

Title
Method for fabricating stackable chip scale semiconductor package
Application Number
9/316997
Publication Number
6235554 (B1)
Application Date
May 24, 1999
Publication Date
May 22, 2001
Inventor
Warren M Farnworth
Nampa
ID, US
Alan G Wood
Boise
ID, US
Salman Akram
Boise
ID, US
Agent
Stephen A Gratton
US
Assignee
Micron Technology
ID, US
IPC
H01L 21/44
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