06230252 is referenced by 92 patents and cites 84 patents.

A scalable multiprocessor system includes processing element nodes. A scalable interconnect network includes physical communication links interconnecting the processing element nodes in an n-dimensional topology, and routers for routing messages between the processing element nodes on the physical communication links. The routers are capable of routing messages in hypercube topologies of at least up to six dimensions, and further capable of routing messages in at least one n dimensional torus topology having at least one of the n dimensions having a radix greater than four, such as a 4×8×4 torus topology.

Title
Hybrid hypercube/torus architecture
Application Number
8/971588
Publication Number
6230252 (B1)
Application Date
November 17, 1997
Publication Date
May 8, 2001
Inventor
Michael B Galles
Los Altos
CA, US
Greg Thorson
Altoona
WI, US
Randal S Passint
Chippewa Falls
WI, US
Agent
Schwegman Lundberg Woessner & Kluth P A
US
Assignee
Silicon Graphics
CA, US
IPC
G06F 13/00
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