A computer aided hardware design system for enabling design of an actual hardware implementation for a digital circuit using a high-level algorithmic programming language. The system converts an algorithmic representation for a hardware design initially created in the high-level programming language, such as ANSI C, to a hardware design implementation, such as an FPGA or other programmable logic or an ASIC. The C-type program representative of the hardware design is compiled into a register transfer level (RTL) hardware description language (HDL) that can be synthesized into a gate-level hardware representation. The system additionally enables simulation of the HDL design to verify design functionality. Finally, various physical design tools can be utilized to produce an actual hardware implementation. The system also permits the use of other non-C-type high-level programming languages by first translating to a C-type program. In contrast to previous hardware design tools, the system compiles all C-type programming language features, including pointers and structures, into synthesizable HDL.