06216252 is referenced by 164 patents and cites 41 patents.

A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications is disclosed. The methodology uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; high level what-if analysis; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure. The methodology includes using estimators for partitioning and evaluating a design prior to logic synthesis. From the structural description, a physical implementation of the device is readily realized.

Techniques for scaling of a model design to provide a scaled design are described whereby parameters of a model design such as size, circuit complexity, interconnection density, number of I/O connections, etc., can be scaled to produce a scaled version of the design. The scaling techniques employ multi-level hierarchical module replication to produce fully-functional scaled designs which closely match the function of the model design. Test vectors for the scaled designs can be readily obtained by altering test vectors for the model design to account for the replicated modules.

Title
Method and system for creating, validating, and scaling structural description of electronic device
Application Number
8/701236
Publication Number
6216252 (B1)
Application Date
August 22, 1996
Publication Date
April 10, 2001
Inventor
Manouchehr Vafai
Los Gatos
CA, US
Doron Mintz
Sunnyvale
CA, US
Carlos Dangelo
Los Gatos
CA, US
Assignee
LSI Logic Corporation
CA, US
IPC
G06F 17/50
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