06212544 is referenced by 273 patents and cites 58 patents.

A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread switch will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive unproductive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.

Title
Altering thread priorities in a multithreaded processor
Application Number
8/958718
Publication Number
6212544 (B1)
Application Date
October 23, 1997
Publication Date
April 3, 2001
Inventor
Andrew Henry Wottreng
Rochester
MN, US
William Thomas Flynn
Rochester
MN, US
John Michael Borkenhagen
Rochester
MN, US
Agent
Karuna Ojanen
US
Assignee
International Business Machines Corporation
NY, US
IPC
G06F 9/46
View Original Source