06209123 is referenced by 391 patents and cites 23 patents.

A method of automatically placing transistors of a folded transistor circuit for synthesizing rows of transistors in a semiconductor layout (

172

). First, an initial placement of transistors is generated (

802

). Next, a candidate move of transistors is selected (

804

). Then the change in cost of the placement resulting from applying the candidate move is evaluated (

806

). A decision is made to accept the candidate move based on the evaluation of its cost (

808

). If accepted, the move is performed (

810

) and the cost of the placement is updated (

812

). Finally, a decision to terminate the process is made (

814

).

Title
Methods of placing transistors in a circuit layout and semiconductor device with automatically placed transistors
Application Number
8/740772
Publication Number
6209123 (B1)
Application Date
November 1, 1996
Publication Date
March 27, 2001
Inventor
Srilata Raman
Austin
TX, US
Mohankumar Guruswamy
Austin
TX, US
Robert L Maziasz
Austin
TX, US
Agent
M Kathryn Braquet Tsirigotis
US
Assignee
Motorola
IL, US
IPC
G06F 17/50
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