06209072 is referenced by 6 patents and cites 41 patents.

A source synchronous interface between a master device and slave device is described. A master device having a plurality of deskew latches is coupled to a slave device via a bus. The master device communicates commands and first timing information to the slave device via the bus. In response, the slave device communicates data and second timing information to the master device via the bus. When data is communicated from the slave device to the master device, the data is stored in one of the plurality of deskew latches until accessed by the master device. The plurality of deskew latches ensure that the master device will always read valid data for the full range of skew of the first and second timing information.

Title
Source synchronous interface between master and slave using a deskew latch
Application Number
8/852438
Publication Number
6209072 (B1)
Application Date
May 6, 1997
Publication Date
March 27, 2001
Inventor
Dilip Sampath
Sunnyvale
CA, US
Manoji Khare
Sunnyvale
CA, US
Bindi Prasad
Los Altos
CA, US
Peter MacWilliams
Aloha
OR, US
Agent
Blakely Sokoloff Taylor & Zafman
US
Assignee
Intel Corporation
CA, US
IPC
G06F 13/00
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