06208180 is referenced by 105 patents and cites 101 patents.

A 2/N mode dock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.

Title
Core clock correction in a 2/N mode clocking scheme
Application Number
9/170997
Publication Number
6208180 (B1)
Application Date
October 13, 1998
Publication Date
March 27, 2001
Inventor
Javed S Barkatullah
Portland
OR, US
Chakrapani Pathikonda
Beaverton
OR, US
Matthew A Fisch
Beaverton
OR, US
Agent
Blakely Sokoloff Taylor & Zafman
US
Assignee
Intel Corporation
CA, US
IPC
H03L 7/00
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