06202125 is referenced by 42 patents and cites 42 patents.

A computer system having a processor-cache protocol supporting multiple cache configurations is described. The computer system has a processor having a cache control circuit to control multiple cache memory circuits. The processor including its cache control circuit is coupled to a cache bus. A second level cache memory is also coupled to the cache bus. The cache control circuit controls the second level cache by issuing commands that are executed by the second level cache.

Title
Processor-cache protocol using simple commands to implement a range of cache configurations
Application Number
8/851845
Publication Number
6202125 (B1)
Application Date
May 6, 1997
Publication Date
March 13, 2001
Inventor
Phil G Lee
Aloha
OR, US
Steve Hunt
Felton
CA, US
Peter MacWilliams
Aloha
OR, US
Gurbir Singh
Portland
OR, US
Bindi Prasad
Los Altos
CA, US
Dan Patterson
Sunnyvale
CA, US
Agent
Blakely Sokoloff Taylor & Zafman
US
Assignee
Intel Corporation
CA, US
IPC
G06F 12/00
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